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9251d-auto-11/12 features supply voltage up to 40v r dson typically 0.8 at 25c, maximum 1.5 at 150c up to 1.0a output current three half-bridge outputs formed by thr ee high-side and three low-side drivers capable of switching loads such as dc motors, bulbs, resistors, capacitors, and inductors pwm capability up to 25khz for each high-side output controlled by external pwm signal no shoot-through current very low quiescent current i vs < 2a in standby mode over total temperature range outputs short-circuit protected selective overtemperature protection for each switch and overtemperature prewarning undervoltage protection various diagnostic functions such as shorted output, open load, overtemperature and power-supply fail detection serial data interface, daisy chain capable, up to 2mhz clock frequency qfn18 package ata6831c triple half-bridge driver with spi and pwm datasheet
ata6831c [datasheet] 9251d?auto?11/12 2 1. description the atmel ? ata6831c provides fully protected driver interfaces designed in soi technology. they are used to allow a microcontroller to control up to three different loads in automot ive and industrial applications. each of the three high-side and three low-side drivers is capabl e of driving currents up to 1.0a. due to the enhanced pwm signal (up to 25khz) it is possible to generate a smooth cont rol of, for example, a dc motor without any noise. the drivers are internally connected to form three half-bridges and can be controlled separately from a stand ard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capac itors and inductors, to be combined. the ic design especially supports the application of h- bridges to drive dc motors. protection is guaranteed with respect to short-circuit conditions, overtemperat ure and undervoltage. various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. automotive qualification (protection against conducted interferences, emc protection and 2-kv esd protection) gives added value and enhanced quality for exacting requiremen ts of automotive applications. figure 1-1. block diagram fault detector fault detector s i h s 2 l s 2 h s 1 l s 1 control logic 5 clk 6 pwm 7 do 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o l d p h 2 p l 2 p h 1 p l 1 p h 3 p l 3 p s f fault detector n. u. n. u. n. u. t p n. u. n. u. n. u. i n h o v l fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs1 10 vs2 11 vcc 9 gnd 18 gnd 17 gnd 14 gnd 8 out3f out3s 2 1 out1f 15 out1s 16 out2f out2s 12 13 o s c
3 ata6831c [datasheet] 9251d?auto?11/12 2. pin configuration figure 2-1. pinning qfn18 table 2-1. pin description pin symbol function 1 out3s used only for final testing, to be connected to out3f 2 out3f half-bridge output 3; formed by internally c onnecting power mos high-side switch 3 and low- side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3 cs chip select input; 5v cmos logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4 di serial data input; 5v cmos logic level input with internal pull-down; receives serial data from the control device; di expects a 16-bit control word with lsb transferred first 5 clk serial clock input; 5v cmos logic level input with internal pull-down; controls serial data input interf ace and internal shift register (f max = 2mhz) 6 pwm pwm input; 5v cmos logic level input with internal pull-down 7 do serial data output; 5v cmos logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontrolle r (lsb transferred first); output will remain tri- stated unless device is selected by cs = low; this allows several ics to operate on only one data-output line 8 gnd ground 9 vcc logic supply voltage (5v) 10 vs1 power supply for output stages out1 and out2; internal supply 11 vs2 power supply for output stages out2 and out3; internal supply 12 out2f half-bridge output 2; formed by internally c onnected power mos high-side switch 2 and low- side switch 2 with internal reverse diodes; short circuit protection; over temperature protection; diagnosis for short and open load 13 out2s used only for final testing, to be connected to out2f 14 pgnd2 power ground out2 15 out1f half-bridge output 1; formed by internally c onnected power mos high-side switch 1 and low- side switch 1 with internal reverse diodes; short circuit protection; over temperature protection; diagnosis for short and open load 16 out1s used only for final testing, to be connected to out1f 17 pgnd1 power ground out1 18 pgnd3 power ground out3 out3s out3f cs di clk pwm out2f vs2 vs1 vcc gnd do pgnd3 pgnd1 out1s out1f pgnd2 out2s 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 13 14
ata6831c [datasheet] 9251d?auto?11/12 4 3. functional description 3.1 serial interface data transfer starts with the falling edge of the cs signal. data must appear at di synchronized to clk and is accepted on the falling edge of the clk signal. the lsb (bit 0, srr) has to be transferred first. execution of new input data is enabled on the rising edge of the cs signal. when cs is high, pin do is in tri-state condition. this output is enabled on the falling edge of cs. output data will change their state with the rising edge of clk and stay stable until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer table 3-1. input data protocol bit input register function 0 srr status register reset (high = reset; the bits psf and ovl in the output data register are set to low) 1 ls1 controls output ls1 (hig h = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 pl1 output ls1 additionally controlled by pwm input 8 ph1 output hs1 additionally controlled by pwm input 9 pl2 see pl1 10 ph2 see ph1 11 pl3 see pl1 12 ph3 see ph1 13 old open load detection (low = on) 14 ocs overcurrent shutdown (high = overcurrent shutdown is active) 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered) srr ls1 hs1 ls2 hs2 ls3 hs3 pl1 ph1 pl2 ph2 pl3 ph3 old ocs si cs di clk do tp s1l s1h s2l s2h s3l s3h n. u. n. u. n. u. n. u. n. u. n. u. ovl inh psf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
5 ata6831c [datasheet] 9251d?auto?11/12 after power-on reset, the input re gister has the following status: the following patterns are used to enable internal test mode s of the ic. do not use these patterns during normal operation. table 3-2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning 1 status ls1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by srr 2 status hs1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by srr 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 ovl over-load detected: set high, when at leas t one output is switched off by a short- circuit condition or an overtemperature ev ent. bits 1 to 6 can be used to detect the affected switch 14 inh inhibit: this bit is controlled by software (bit si in input register) high = standby, low = normal operation 15 psf power-supply fail: undervoltage at pin vs detected bit 15 si bit 14 ocs bit 13 old bit 12 ph3 bit 11 pl3 bit 10 ph2 bit 9 pl2 bit 8 ph1 bit 7 pl1 bit 6 hs3 bit 5 ls3 bit 4 hs2 bit 3 ls2 bit 2 hs1 bit 1 ls1 bit 0 srr h h h l l l l l l l l l l l l l bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) h h h h h l l l l l l l l l l l h h h l l h h l l l l l l l l l h h h l l l l h h l l l l l l l
ata6831c [datasheet] 9251d?auto?11/12 6 3.2 power-supply fail if undervoltage is detect ed at pin vs, the power-supply fail bit (psf) in th e output register is set and all outputs are disabl ed. to detect an undervoltage, its duration has to last longer than the undervoltag e detection delay time t duv . the outputs are enabled immediately when the supply voltage returns to the normal operational value. the psf bi t stays high until it is reset by the srr bit in the input register. 3.3 open-load detection (available for h-bridge configuration only) if the open-load detection bit (old) is set to low, a pull-up cu rrent for each high-side switch of typically 2.5ma and a pull- down current for each low-side switch of typically 9ma is turned on (open-load detection current iout1-3). the open load condition of all the outputs is indicated in the spi output register bit 1-6. activating an output stage with the old bit set to lo w disables the open-load function for this output. figure 3-2. open load detection in h-bridge configuration operating open load and short circuit detection in h-brid ge configuration requires the following command sequence: step #1 a. low side check input: hsx = 0, lsx = 1 , hsy = 0, lsy = 0, old = 0 b. feedback: lsy = 1 indicates ?motor connected? lsy = 0 indicates ?motor connection fail?, open load step #2 a. high side check input: hsx = 1 , lsx = 0, hsy = 0, lsy = 0, old = 0 b. feedback: hsy = 1 indicates ?motor connected? hsy = 0 indicates ?motor connection fail?, open load the maximum h-bridge load resistance for proper load detection is 170 . both conditions step #1 and #2 need to be fulfilled. vs gnd hsx outx outy hsy lsx lsy m
7 ata6831c [datasheet] 9251d?auto?11/12 3.4 overtemperature protection if the junction temperatur e of one or more output stages exceeds the thermal prewarning threshold, t jpw set , the temperature prewarning bit (tp) in the output register is set. when t he temperature falls below the th ermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without trans ferring a complete 16-bit data word. the status of tp is available at pin do with the falling edge of cs. after the microc ontroller has read this information, cs is set high and the data transfer is interrupted without affecting the status of input and output registers. if the junction temperature of an output st age exceeds the thermal shutdown threshold, t jswitch off , the affected output is disabled and the corresponding bit in the output register is se t to low. additionally, the overl oad detection bit (ovl) in the output register is set. the out put can be enabled again when the temperature fa lls below the thermal shutdown threshold, t jswitch on , and the srr bit in the input register is set to high. t he hysteresis of thermal prew arning and shutdown threshold avoids oscillations. 3.5 short-circuit protection the output currents are limited by a current regulator. overcurrent detection is acti vated by writing a hi gh to the overcurrent shutdown bit (ocs) bit in the input register . when the current in an output stage e xceeds the overcurrent limitation and shut- down threshold, it is switched off, following a delay time (t dsd ). the over-load detection bit (ovl) is set and the corresponding status bit in the output register is set to low. for ocs = low, the overcurrent shutdown is inactive and the ovl bit is not set by an overcurrent. by writing a high to the srr bit in the input register the ovl bit is reset and the disabled outputs are enabled. 3.6 inhibit the si bit in the input register has to be set to zero to inhibit the atmel ? ata6831c. in this state, all output stages are then turned off but the se rial interface remains active. the current consumption is reduce d to less than 2a at pin vs and less than 100a at pin vcc. the output stages can be reactivated by setting bit si to ?1?. 3.7 pwm mode the common input for all six outputs is pin pwm ( figure 3-3 ). the selection of the outputs, which are controlled by pwm, is done by input data register plx or phx. in addition to the pwm input register, the corresponding input registers hsx and lss have to be set. switching the high side outputs is possible up to 25khz, low side switches up to 8khz. figure 3-3. output control by pwm bit lsx/hsx bit plx/phx pin outx pin pwm
ata6831c [datasheet] 9251d?auto?11/12 8 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters pin symbol value unit supply voltage 10, 11 v vs ?0.3 to +40 v supply voltage t < 0.5s; i vs > ?2a 10, 11 v vs ?1 v logic supply voltage 9 v vcc ?0.3 to +7 v logic input voltage 3, 4, 5, 6 v cs , v di , v clk , v pwm ?0.3 to v vcc + 0.3 v logic output voltage 7 v do ?0.3 to v vcc + 0.3 v input current 3, 4, 5, 6 i cs , i di , i clk , i pwm ?10 to +10 ma output current 7 i do ?10 to +10 ma output current 2, 12, 15 i out1 , i out2 , i out3 internally limited, see output specification output voltage 2, 12, 15 i out1 , i out2 , i out3 ?0.3 to +40 v reverse conducting current (t pulse = 150s) 2, 12, 15 i out1 , i out2 , i out3 17 a junction temperature range t j ?40 to +150 c storage temperature range t stg ?55 to +150 c 5. thermal resistance parameters test conditions symbol value unit thermal resistance fr om junction to case r thjc 5 k/w thermal resistance from junction to ambient depends on the pc board r thja 40 k/w 6. operating range parameters symbol value unit supply voltage v vs v uv (1) to 40 v logic supply voltage v vcc 4.75 to 5.25 v logic input voltage v cs , v di , v clk , v pwm ?0.3 to v vcc v serial interface clock frequency f clk 2 mhz pwm input frequency f pwm max. 25 khz junction temperature range t j ?40 to +150 c note: 1. threshold for undervoltage description
9 ata6831c [datasheet] 9251d?auto?11/12 7. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) esd s 5.1 2kv cdm (charge device model) esd stm5.3.1 500v note: 1. test pulse 5: v smax = 40v 8. electrical characteristics 7.5v < v vs < 40v; 4.75v < v vcc < 5.25v; inh = high; ?40c < t j < 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current vs v vs < 20v, si = low 10, 11 i vs 1 2 a a 1.2 quiescent current vcc 4.75v < v vcc < 5.25v, si = low 9 i vcc 60 100 a a 1.3 supply current vs v vs < 20v normal operating, all outputs off, input register bit 13 (old) = high 10, 11 i vs 4 6 ma a 1.4 supply current vcc 4.75v < v vcc < 5.25v, normal operating 9 i vcc 350 650 a a 1.5 discharge current vs v vs = 32.5v, inh = low 10, 11 i vs 0.5 5.5 ma a 1.6 discharge current vs v vs = 40v, inh = low 10, 11 i vs 2.5 14 ma a 2 undervoltage detection, power-on reset 2.1 power-on reset threshold 9 v vcc 3.2 3.9 4.4 v a 2.2 power-on reset delay time after switching on v vcc t dpor 30 95 190 s a 2.3 undervoltage-detection threshold v vcc =5v 10, 11 v uv 5.6 7.0 v a 2.4 undervoltage-detection hysteresis v vcc = 5v 10, 11 v uv 0.6 v a 2.5 undervoltage-detection delay time t duv 10 40 s a 3 thermal prewarning and shutdown 3.1 thermal prewarning set t jpw set 120 145 170 c b 3.2 thermal prewarning reset t jpw reset 105 130 155 c b 3.3 thermal prewarning hysteresis t jpw 15 k b 3.4 thermal shutdown off t j switch off 150 175 200 c b *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
ata6831c [datasheet] 9251d?auto?11/12 10 3.5 thermal shutdown on t j switch on 135 160 185 c b 3.6 thermal shutdown hysteresis t j switch off 15 k b 3.7 ratio thermal shutdown off/thermal prewarning set t j switch off/ t jpw set 1.05 1.2 b 3.8 ratio thermal shutdown on/thermal prewarning reset t j switch on/ t jpw reset 1.05 1.2 b 4 output specification (out1 to out3) 4.1 on resistance i out1-3 = ?0.9a 2, 12, 15 r dson1-3h 1.5 a 4.2 i out1-3 = ?0.9a 2, 12, 15 r dson1-3l 1.5 a 4.3 high-side output leakage current v out 1-3 h = 0v , output stages off 2, 12, 15 i out1-3h ?15 a a 4.4 low-side output leakage current v out 1-3 l = v vs, output stages off 2, 12, 15 i out1-3l 300 a a 4.5 high-side switch reverse diode forward voltage i out = 1.5a 2, 12, 15 v out1-3 ? v vs 2 v a 4.6 low-side switch reverse diode forward voltage i out 1-3 l = ?1.5a 2, 12, 15 v out1-3l 2 v a 4.7 high-side overcurrent limitation and shutdown threshold 7.5v < v vs < 20v 2, 12, 15 i out1-3 1.0 1.3 1.7 a a 4.8 low-side overcurrent limitation and shutdown threshold 7.5v < v vs < 20v 2, 12, 15 i out1-3 ?1.7 ?1.3 ?1.0 a a 4.9 high-side overcurrent limitation and shutdown threshold 20v < v vs < 40v 2, 12, 15 i out1-3 1.0 1.3 2.0 a a 4.10 low-side overcurrent limitation and shutdown threshold 20v < v vs < 40v 2, 12, 15 i out1-3 ?2.0 ?1.3 ?1.0 a a 4.11 overcurrent shutdown delay time t dsd 10 40 s a 4.12 high-side open load detection current input register bit 13 (old) = low, output off v vs = 13v, v out 1-3 = 0v 2, 12, 15 i out1-3h 1 2.5 4 ma a 4.12a high-side open load detection threshold level input register bit 13 (old) = low, output off v vs = 13v, i out1-3 =0ma 2, 12, 15 v out1-3_old_hth v vs ? 3.5v v vs ? 2.5v v vs ? 1v v a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.75v < v vcc < 5.25v; inh = high; ?40c < t j < 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
11 ata6831c [datasheet] 9251d?auto?11/12 4.13 low-side open load detection current input register bit 13 (old) = low, output off v vs = 13v, v out 1-3 = 13v 2, 12, 15 i out1-3l ?6 ?9 ?11 ma a 4.13a low-side open load detection threshold level input register bit 13 (old) = low, output off v vs = 13v, i out1-3 =0ma 2, 12, 15 v out1-3_old_lth 0.5 1.5 2.5 v a 4.14 open load detection current ratio i out1-3l /i out1-3h 2 3 4 4.15 high-side output switch on delay (1),(2) v vs = 13v r load =30 t don 20 s a 4.16 low-side output switch on delay (1),(2) v vs = 13v r load =30 t don 20 s a 4.17 high-side output switch off delay (1),(2) v vs =13v r load = 30 t doff 20 s a 4.18 low-side output switch off delay (1),(2) v vs =13v r load = 30 t doff 3 s a 4.19 dead time between corresponding high-side and low-side switches v vs =13v r load = 30 t don ? t doff 1 s a 4.20 t dpwm low-side switch (3) v vs = 13v r load = 30 t dpwm = t don ? t doff 20 s a 4.21 t dpwm high-side switch (3) v vs = 13v r load = 30 t dpwm = t don ? t doff -5 5 s a 5 logic inputs di, clk, cs, pwm 5.1 input voltage low-level threshold 3, 4, 5, 6 v il 0.3 v vcc v a 5.2 input voltage high-level threshold 3, 4, 5, 6 v ih 0.7 v vcc v a 5.3 hysteresis of input voltage 3, 4, 5, 6 v i 50 700 mv a 5.4 pull-down current pins di, clk, pwm v di , v clk, v pwm = v vcc 4, 5, 6 i pd 10 65 a a 5.5 pull-up current pin cs v cs = 0v 3 i pu ?65 ?10 a a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.75v < v vcc < 5.25v; inh = high; ?40c < t j < 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
ata6831c [datasheet] 9251d?auto?11/12 12 6 serial interface ? logic output do 6.1 output-voltage low level i dol = 2ma 7 v dol 0.4 v a 6.2 output-voltage high level i dol = ?2ma 7 v doh v vcc ? 0.7v v a 6.3 leakage current (tri-state) v cs = v vcc 0v < v do < v vcc 7 i do ?10 10 a a 7 inhibit input ? timing 7.1 delay time from standby to normal operation t dinh 100 s a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.75v < v vcc < 5.25v; inh = high; ?40c < t j < 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and switch on/off output stages to 90% of final level. device not in standby for t > 1ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode. 9. serial interface timing no. parameters test conditions pin timing chart no. (1) symbol min. typ. max. unit type* 8 serial interface timing 8.1 do enable after cs falling edge c do = 100pf 7 1 t endo 200 ns d 8.2 do disable after cs rising edge c do = 100pf 7 2 t disdo 200 ns d 8.3 do fall time c do = 100pf 7 - t dof 100 ns d 8.4 do rise time c do = 100pf 7 - t dor 100 ns d 8.5 do valid time c do = 100pf 7 10 t doval 200 ns d 8.6 cs setup time 3 4 t cssethl 225 ns d 8.7 cs setup time 3 8 t cssetlh 225 ns d 8.8 cs high time 3 9 t csh 500 ns d 8.9 clk high time 5 5 t clkh 225 ns d 8.10 clk low time 5 6 t clkl 225 ns d 8.11 clk period time 5 - t clkp 500 ns d 8.12 clk setup time 5 7 t clksethl 225 ns d 8.13 clk setup time 5 3 t clksetlh 225 ns d 8.14 di setup time 4 11 t diset 40 ns d 8.15 di hold time 4 12 t dihold 40 ns d *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
13 ata6831c [datasheet] 9251d?auto?11/12 figure 9-1. serial interface timing with chart number 1 do cs clk cs do clk output do: high level = 0.8 x v cc , low level = 0.2 x v cc inputs di, clk, cs: high level = 0.7 x v cc , low level = 0.3 x v cc di 11 5 6 8 10 12 3 9 2 4 7
ata6831c [datasheet] 9251d?auto?11/12 14 10. application circuit figure 10-1. application circuit 10.1 application notes connect the blocking capacitors at v vcc and v vs as close as possible to the power supply and gnd pins. recommended value for capacitors at v vs : electrolytic capacitor c > 22f in parallel with a ceramic capacitor c = 100nf. the value for the electrolytic capacitor depends on external loads, conducted inte rferences, and the reve rse conducting current i out1,2,3 . recommended value for capacitors at v vcc : electrolytic capacitor c > 10f in parallel with a ceramic capacitor c = 100nf. to reduce thermal resistance, place cooling areas on the pc b as close as possible to the gnd pins and to the die pad. fault detector fault detector s i h s 2 l s 2 h s 1 l s 1 control logic 5 clk 6 pwm 7 do 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o l d p h 2 p l 2 p h 1 p l 1 p h 3 p l 3 p s f fault detector n. u. n. u. n. u. t p n. u. n. u. n. u. i n h o v l fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs1 10 vs2 11 vcc 9 gnd 18 gnd 17 gnd 14 gnd 8 out3f 2 out1f 15 out2f 12 o s c v cc v cc u5021m watchdog reset trigger micro- controller m m v cc + v s 13v v batt 5v v cc byv28 + 1 13 16
15 ata6831c [datasheet] 9251d?auto?11/12 12. package information 11. ordering information extended type number package remarks ata6831c-piqw qfn18, 4mm 4mm taped and reeled, pb-free package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5133.01-4 3 05/20/11 package: vqfn_4x4_18l exposed pad 2.7x3.175 common dimensions (unit of measure = mm) min nom note max symbol specifications according to din technical drawings 0.02 0.05 0.0 a1 44.05 3.95 e 0.23 0.3 0.16 b 0.5 bsc e 0.4 0.5 0.3 l 0.25 0.3 0.2 k 3.175 3.225 3.125 e2 2.7 2.75 2.65 d2 44.05 3.95 d 0.2 0.25 0.15 a3 0.9 1 0.8 a top view side view bottom view dimensions in mm not indicated tolerances 0.05 d 18 1 6 pin 1 id e a3 a a1 z 10:1 e b d2 k 13 18 6 1 7 12 e2 l 0.175 z
ata6831c [datasheet] 9251d?auto?11/12 16 13. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9215d-auto-11/12 ? section 3.3 ?open-load detection (available for h-bridge configuration only)? on page 6 updated 9215c-auto-06/11 ? package information: drawing changed 9215b-auto-01/11 ? features on page 1 changed ? section 3.6 ?inhibit? on page 7 changed ? section 8 ?electrical characteristics? number 1.1 on page 9 changed
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